1. Technical Field
The present invention relates to a semiconductor device and a method of manufacturing the same.
2. Related Art
In recent years, there has been an increasing trend of using metal-insulator-metal type (MIM-type) capacitor element, having parasitic resistance and parasitic capacitance extremely smaller than those of conventional MOS-type capacitor element. One-chip configuration having such MIM-type capacitor element integrated into a logic device has also been developed. To realize this sort of configuration, structures and processes of manufacturing of both devices should be harmonized. The logic device generally adopts a multi-layer structure. A critical technical issue resides therein is how to harmonize the structure and processes of the MIM-type capacitor element to the multi-layer structure in an appropriate manner. From this point of view, there has been developed a process by which electrodes in the MIM-type capacitor element are fabricated by a technique similar to those for the multi-layer structure of the logic device.
As described in Japanese Laid-Open Patent Publication No. 2003-258107, the conventional MIM-type capacitor element often formed in a region having no lower interconnect formed therein, and rarely formed above the region having a high density of fine interconnects formed therein.
However, elements have more advanced in terms of degree of integration in these days, and the situation demands that the MIM-type capacitor element should be formed also above the region having a high density of fine interconnects formed therein, in order to reduce area of the semiconductor device. The requirement raises problems below.
The multi-layered interconnect of the logic devices in these days generally adopts copper interconnect having low resistivity. Damascene process is widely adopted to form the copper interconnect. In the damascene process, first, trenches are formed in an insulating film such as a silicon oxide film, and a barrier metal layer for blocking diffusion of copper is formed. The trenches are then filled with copper typically by plating, and the copper is then polished by chemical mechanical polishing (CMP) to thereby form the interconnect. On the copper interconnect, a diffusion barrier film such as a SiCN film is formed, wherein the interconnect produces hillocks on the surface thereof, due to annealing carried out as pretreatment of formation of the diffusion barrier film, and thereby sharp differences in height may be produced on the surface of the interconnect. The difference in height is reflected also to the diffusion barrier film formed thereon, and is reflected further to the insulating interlayer and the capacitor element formed further thereon. Such sharp differences in height remained unremoved on the capacitor element may cause short-circuiting between the lower interconnect and the capacitor element, due to contact between the top surfaces of the hillocks on the lower interconnect and the lower electrode of the capacitor element, or may degrade margin for short-circuiting due to close disposition of the top surfaces of the hillocks and the lower electrode, even though this would not result in actual short-circuiting. This may be causative of degradation in yield ratio of the MIM-type capacitor elements, and degradation in reliability of use.
This nonconformity may occur, not only for the case where the MIM-type capacitor element is used in the upper region, but also for the case of general multi-layered interconnect having the damascene structure. In other words, the difference in height, ascribable to the hillocks on the lower interconnect in the process of forming the multi-layered interconnect, is reflected also to the upper interconnect. As a consequence, short-circuiting between the upper and lower interconnects due to contact between the hillocks of the lower interconnect and the upper interconnect, and degradation in the margin for short-circuiting would occur.